Chris Jenkins

Chris is a Contributing Writer at MacRumors. An electrical engineer by trade, he likes to spend his free time with family and a hockey game or two.



Throttling in New i9 MacBook Pros Appears to be Due to Power Delivery Chip

A user posting on reddit and in the MacRumors forums has given a detailed account of their findings and attempts to circumvent the throttling previously discovered on the new MacBook Pro 15" models featuring the six-core i9 Intel CPUs. The user goes on to explain that one of the internal power limits set for the device may not be appropriate for the power draw of the CPU and identical to previous MacBook Pro models, causing the power delivery chip (known as a voltage regulation module, or VRM) to report an over power condition that forces the clock of the CPU down to scale back power. This sets up the same conditions to allow throttling to occur once again. These conditions may be presenting themselves due to the new six-core design of the i9 CPU featured here. While Intel increased the core count of the CPU, they did not increase the thermal design power (TDP), or the amount of dissipated power manufacturers should plan to have to cool for a proper CPU design. This is an issue because this number usually reflects normal usage, and does not account for turbo modes. It's also likely it can exceed the draw of previous four core CPUs given the similarity of clock speeds and process nodes they are featured on. A method for tuning this limit is provided in the post, but it requires executing a command manually or via script each time the computer boots, and would likely void the warranty if Apple technicians discovered it. Still, the user posts results of benchmarks showing successive runs with no throttling. Manufacturers will always quote likely reduced component

Patent Applications Reveal Apple's Research Into 3D Chip Packaging

Apple's persistent quest for better performance, longer battery life, and slimmer form factors appears to be driving its research into advanced chip packaging technologies. So-called "2.5D" and "3D" packaging methods stand to offer significant gains in all of these areas by increasing memory bandwidth, reducing power consumption, and freeing up space for higher-capacity batteries. Apple has been an aggressive adopter of new device packaging methods, mostly thanks to integrated fan-out (InFO) innovations provided by foundry partner TSMC. TSMC's success has spurred it into further developing and diversifying its packaging offerings, and TSMC has emerged as an industry leader in packaging techniques. While versions of TSMC's InFO packaging have brought performance improvements to Apple devices, such as better thermal management and improved package height, it has largely not been a direct enabler of improved electrical performance. This is set to change with future packaging techniques and is already seen in some products that utilize interposers for higher density interconnects to on-package memory, such as High Bandwidth Memory (HBM). The primary memory candidate for inclusion in such a package would be conforming to the Wide I/O set of standards described by JEDEC, and mentioned by name in several of the patents. This memory improves on LPDDR4 by increasing the number of channels and reducing the transfer speed per channel, thus increasing the overall bandwidth but lowering the energy required per bit. Interposers do, however, pose several issues for

Apple's Workforce Growth in Oregon Could Point to Desktop-Class CPU Ambitions

Yesterday, we reported on Apple's opening of a new technology hub in Oregon, along with the hiring of several former senior Intel engineers. Oregon is the site of Intel's Hillsboro facilities, featuring the chipmaker's leading-edge 14 nm and 10 nm foundries, as well as CPU design expertise for desktop-class processor thermal budgets. A search of Apple's open positions indicated there were several openings for hardware engineers with backgrounds in computer architecture and silicon verification. Intel's Ronler Acres campus in Hillsboro (Randy L. Rasmussen/The Oregonian) Digging deeper into these job positions reveals keywords indicating performance validation in non-iOS workloads, as well as a heavy focus on memory concepts such as memory controllers, memory hierarchy, and cache coherency protocols. The focus on the memory subsystem is significant because this is one area where mobile device and PC form factor usage models differ based on their power consumption profiles, along with PCs featuring tools that can stress a memory system in ways not typically seen in mobile device workloads. PC systems also tend to feature much higher memory bandwidths, due to both wider memory busses and higher memory clocks. Apple is often rumored to be working on an ARM-based MacBook, but such a device would likely feature some variant of LPDDR memory seen in Apple's mobile devices, as well as Apple's entire line of MacBooks. This means that Apple already has the necessary memory controller designs to interface with LPDDR memory. Apple is also no stranger to the 128-bit memory

Intel Foundries Continue to Face Issues and Another Spectre-Like Vulnerability Disclosure May Be Looming

Despite positive first quarter results for 2018, Intel faces continuing issues with its foundries, both with the oft-delayed 10nm, as well as its own modem production in 14nm. Intel revealed in the earnings conference call that volume 10nm manufacturing had been delayed to 2019, without specifying which part of the year. The debut of Intel's 10nm process has been a particular sore spot, with the forthcoming Whiskey Lake set to be the fifth new architecture debut in the 14nm process. Prior to 14nm, Intel had maintained a two architecture, "tick-tock" strategy for its processors, where a new foundry node denoted a small architecture update over the previous processor as a "tick," and a more significant architectural evolution as a "tock" on a matured process. We first reported on the demise of the tick-tock strategy in 2016. Things have only grown worse for Intel since then as 10nm has faced further delays. To put this delay in perspective, Intel's original roadmaps had 10nm technology debuting in 2015. There are several reasons for the delay, but Intel CEO Brian Krzanich explained that some features in Intel's 10nm process require up to five or six multi-pattern steps, whereas other competing foundries are known for up to four steps in 10nm or 7nm processes. This development has consequences for Intel, its customers, and its competitors. First, Intel has lost the technology advantage it once held over the rest of the semiconductor industry. While you cannot compare the dimension in the node name directly across foundries, competitors such as TSMC, Samsung, and

TSMC Details Technology Roadmap With Multiple Offerings to Benefit Future Apple Devices

As part of its recent Q1 earnings call, TSMC announced that its 7-nanometer FinFET process node has entered into high volume manufacturing (HVM), meaning we could see consumer devices featuring the process as soon as the second half of this year. Previous reports indicated that TSMC is expected to have sole production responsibility for Apple's upcoming A12 chip and its variants expected to debut in new iPhone and iPad products starting this fall. The 7nm node (referred to as CLN7FF, 7FF, or simply N7) is expected to have an approximate 40 percent power and area benefit over TSMC's 10nm FinFET process, utilized in Apple's A11 processors. Additionally, as reported by EETimes, TSMC has offered insight into its technology roadmap, both for its silicon processes and for its device packaging technologies. TSMC is believed to have wrested sole ownership of production for Apple's processors away from the dual-sourcing arrangement with Samsung due to its advancements in wafer-level packaging. (What also went largely unnoticed at the time was TSMC's introduction of land-side capacitors attached directly to the substrate.) Building on the packaging leadership established with its InFO packaging offerings, TSMC has now announced six new packaging types aimed at a variety of devices and applications. The InFO technique is getting four cousins. Info-MS, for memory substrate, packs an SoC and HBM on a 1x reticle substrate with a 2 x 2-micron redistribution layer and will be qualified in September. InFO-oS has a backside RDL pitch better matched to DRAM and is ready now.

Prime Real Estate: The Fight for Space in the iPhone X

As the launch of Apple's iPhone X approaches tomorrow, eager users are set to enjoy battery life normally reserved for Apple's Plus-size form factors in a phone more closely resembling a non-Plus variant in its dimensions. The reason for this advancement is not an energy density development, but rather a smaller printed circuit board (PCB) inside the iPhone X, according to a February report from KGI Securities. 深圳的朋友拆了,還真的兩個電池 pic.twitter.com/7wzrBLVsFy— Anson Chen ☂ (@AnsonChen) November 2, 2017 This smaller PCB is thanks to a technology referred to as substrate-like PCBs, or SLP. Depictions from the report show a PCB with more layers than a traditional iPhone PCB thanks to application processor and RF signal-chain dedicated PCBs married via an interposer, creating a layer stackup nearly twice that of a conventional iPhone PCB. However, this doesn't come close to telling the whole story. While a new PCB stackup may offer some more flexibility in component placement, it's important to remember that the opposite side of the board from the A11 isn't empty in an iPhone 8. There are plenty of components there too — the NFC chip, display drivers, Wi-Fi combo chips, and power management ICs have all often found their homes directly opposite the workhorse application processor. After all, 4.7-inch iPhones and their 5.5-inch "Plus" siblings have similarly sized PCBs, with battery capacity suffering as a direct result in the smaller phones. Herein lies the real problem in trying to improve battery life in these smaller form factors.

iPhone 8 Shows Modest Improvements in Cellular Network Bandwidth Tests

With a number of iPhone 8 and 8 Plus devices now in the hands of users, Ookla's network benchmarking suite Speedtest.net has been able to gather data on how the latest iPhones are performing compared to previous-generation models and has shared details with PCMag. Based on data collected by Ookla, improvements appear to be around the 10 percent mark for most users, but users in Australia could expect up to nearly 25 percent faster speeds thanks to their network structure. Those users can expect up to the full 80 MHz carrier aggregation bandwidth in the phone due to Telestra's use of the appropriate bands. iPhone 8 download speeds compared to previous generations Beyond speed comparisons to previous-generation iPhones, PCMag also compares the iPhone 8's cellular architecture to competing phones, such as the Galaxy S8.The iPhone 8 is missing one of the components needed for gigabit LTE, or LTE category 16, in the US. The Qualcomm X16 modem can do Category 16, as we've seen on the Galaxy S8 and Moto Z2 Force. The phone supports 256QAM encoding and 4x carrier aggregation to 80MHz of spectrum, but not 4x4 MIMO antennas, which would improve both speed and signal strength. In theory, that would make this an 800Mbps phone, also known as LTE category 15.The lack of 4x4 MIMO antennas is something we touched on at MacRumors on Tuesday. While the Qualcomm and Intel modems in the new iPhones are likely more power efficient, the cellular front-end and back-end supporting them are largely unchanged in structure from the iPhone 7 models. The article goes on to point out can that

iPhone 8 Teardowns Reveal Advanced Modems Likely Selected for Power Improvements

Apple released the iPhone 8 and iPhone 8 Plus on Friday, September 22, and device teardowns were underway within hours, courtesy of iFixit and TechInsights. The firms received different models for teardown, with iFixit's model featuring a Qualcomm baseband while TechInsights' featured an Intel modem, continuing Apple's trend of opting for Intel modems in phones which do not require CDMA network support. The baseband parts in each iPhone were revealed to be new chips from their respective vendors, with the CDMA phone featuring Qualcomm's new X16 gigabit-class modem and the Intel-based model featuring the similarly new XMM 7480 modem. Each model also included an update to the transceiver module to go along with the modem, but the functional changes in the RF signal chain mostly stopped there. Qualcomm X16 and X12 feature comparison In addition to higher peak speeds compared to their predecessors, both of these modems offer other potential benefits. Comparing the network compatibility pages of the iPhone 7 against the iPhone 8 shows that the bands supported are largely unchanged, and this is reflected in the small changes to the power amplifier modules (PAMs) found within the RF chain. Besides gigabit-level peak theoretical speeds, the X16 modem brings several other advances, including up to 4x carrier aggregation for a total bandwidth of up to 80 MHz compared to the 60 MHz found in the MDM9645M (X12) powering the iPhone 7. Qualcomm's X16 modem also supports T-Mobile US's new 600 MHz LTE spectrum, Band 71. Apple does not list support for Band 71 on the model sold

Apple's Chip Partner TSMC Shares Details on 7nm Node and Advanced InFO Package Process for 2018

At the Open Innovation Platform Ecosystem Forum in Santa Clara on Wednesday, chip foundry TSMC provided an update (via EE Times) on the progress of its forthcoming technology nodes, several of which would be candidates for upcoming Apple chips. Most notably, the company's first 7-nanometer process node has already had several tape-outs (finalized designs) and expects to reach volume capacity in 2018. TSMC's 10 nm node, which first showed up in Apple's A10X chip in the iPad Pro, followed by the A11, has been fraught with issues (paid link) such as low chip yield and performance short of initial expectations. TSMC looks to change its fortune with the new 7 nm node, which would be suitable for the successor to the A11 chip given current timelines. In addition to the 7 nm node, TSMC also shared information on the follow-up revision to this node, dubbed, N7+. Featuring the long-beleaguered Extreme Ultraviolet Lithography (EUV), the revision would promise 20 percent better density, around 10 percent higher speeds, or 15 percent lower power with other factors held constant. While EUV has faced delays for over a decade at this point, it seems to finally be coming to fruition, and a 2019 volume availability update would allow Apple to update its chip process in subsequent years yet again. Apple had previously updated process nodes with every iPhone since the transition to 3GS before being forced to use TSMC's 16 nm node in consecutive years with the A9 and A10. Moving forward, that annual cadence is again in jeopardy as chip foundries deal with the realities of physics and

A11 Chip's 6-Core Architecture Highlights Apple's Continuing Push Into Heterogeneous Computing

In the recent leak of information from Apple, a device tree shared by Steven Troughton-Smith and containing information specific to the iPhone X was used to glean CPU code names, presence of an OLED display, and information on many other things. Contained within that information were also specific details regarding the architecture behind Apple's new CPU cores, dubbed "Mistral" and "Monsoon." From this, we know that the A11 contains four Mistral cores and two Monsoon cores, and it's worth taking a technical look at what Apple might be up to with this new chip. Leaked A11 chip While the two Monsoon cores are clear follow-ons to the two large "Hurricane" cores in the A10, the Mistral cores double the small core count of two "Zephyr" cores in the A10. September 2016 event slide on the two Zephyr cores in the A10 Annotated die shots ultimately revealed that the small Zephyr cores appeared to be embedded within the larger Hurricane cores, taking advantage of their geographic location by sharing memory structure with the Hurricane cores. Chipworks/TechInsights annotated A10 die photo showing small Zephyr cores embedded within large Hurricane cores (right) The Mistral cores appear to be a departure from the above scheme, at the very least in that they have doubled in count. Specific references in the device tree are also made to memory hierarchy, suggesting that they contain independent L2 caches, meaning the Mistral cores could be more independent than their A10 ancestors. This independence is underscored by the fact that the Mistral cores share a common

A Closer Look at Apple's CPU Improvements for iPhone 7 and Apple Watch

At last Wednesday's media event, Apple introduced two new processors - the A10 Fusion for iPhone 7 and 7 Plus and the S2 for Apple Watch Series 2. Although Apple only briefly covered the S2 during the presentation, it did spend a good deal of time talking about A10 Fusion. The 'Fusion' suffix refers to the heterogeneous architecture that the A10 features, which has two high-power, high-throughput cores and two much smaller cores that are more power efficient. Apple also introduced another very important piece of standalone silicon in its new AirPods, dubbed the W1 chip. In total, this represents a great deal of engineering work done by Apple over the last year, and the A10 is the most significant to Apple's system-on-a-chip (SoC) line since the company's transition to 64-bit. Apple unveiled the biggest technical changes featured in the A10 at the very beginning, boasting a four-core CPU with 3.3 billion transistors. While Apple never disclosed a transistor count for the A9, it very likely fell somewhere in the middle between the 2 billion count on the A8 and the 3.3 billion of the new A10. A transistor count well under 3 billion seems probable for the A9; otherwise it would have been worth boasting about on its own. The 3.3 billion number for the A10 is well over 50 percent larger than the A8, and the large jump is likely mostly thanks to the addition of two new, albeit small, CPU cores along with a greatly enhanced image signal processor (ISP). Apple also disclosed that the GPU remains a six-cluster design, while benchmarks suggest that the L1 and L2 cache

Leaked iPhone 7 Logic Boards Suggest Intel Modem, Other Component Tweaks

Last week, MacRumors covered photos of what appear to be the front and rear of bare iPhone 7 logic boards, and since that time we've been able to study these boards and compare them to previous iPhone generations' bare and populated logic boards. Comparing the boards with existing component offerings and information suggests that Apple has indeed moved on from Qualcomm as its baseband modem supplier and switched to Intel for the upcoming iPhone generation. This does not preclude Apple from having other versions of the iPhone 7 or 7 Plus logic boards which feature a Qualcomm modem, such as an international model with differing LTE band options, as has been rumored. Leaked iPhone 7 logic board with Intel modem location annotated The image above shows the previously leaked and annotated logic board front with the probable location of the Intel baseband modem annotated. The pad pattern for the part in this location is markedly different than the pad pattern for the Qualcomm MDM9635, as shown in iFixit's parts catalog. The pad pattern of this mystery part also appears to match the dimensions listed on Intel's website for similar baseband modem offerings to the rumored XMM 7360 design solution.

How TSMC Won Back Exclusivity With Apple for the A10 Chip in iPhone 7

Last year, MacRumors covered the potential reasoning for Apple's rumored return to having a single partner for Apple A-series chip production with the A10 after having both Samsung and TSMC produce versions of the Apple A9. Since then, TSMC confirmed in conference call comments that its chip packaging changes have led to improvements of 20 percent in both speed and packaging thickness and 10 percent in thermal performance. This has a number of implications for future device performance and future foundry partner selection for Apple. First, it is helpful to understand why InFO-WLP (Integrated Fan-Out Wafer-Level Packing) is such an important development for Apple's mobile processors. Typically, chips as large as CPUs or mobile SoCs have been attached via "flip-chip" methods which attach an array of inputs and outputs to a package substrate via solder bumps, ultimately enabling it to be attached to a printed circuit board (PCB) for device integration. From the start, this is a compromise, as it would be preferable to attach a silicon die directly to the PCB to minimize height and reduce the lengths of interconnects between components. A number of technical limits in areas such as interconnect pitch, board produceability, and damage due to board warpage typically prevent this direct attachment. The above problem had previously been circumvented for smaller I/O count components with a similar concept called Fan-In Wafer-Level Packing, where smaller dies are allowed to route their inputs and outputs in an area roughly the same area as the die. TSMC is just one of

New Semiconductor Processes Offer Power Efficiency Opportunities for Apple Watch

One of the key challenges for Apple in developing the Apple Watch was figuring out how to maintain acceptable battery life for the device in the face of power-hungry components such as the main processor and display. With watchOS 3 introduced at WWDC in June, Apple showed off the ability to allow multiple Apple Watch apps to remain active and refresh in the background, acknowledging that its initial approach to managing power and other system resources was conservative but that real-world experience had shown the device could handle more demanding tasks. In addition to software improvements, future generations of the Apple Watch will need to become more efficient on the hardware level, with new versions of the S1 chip that serves as the brains of the device being a primary target for improvement. With that in mind, we've taken a technical look at what the future could hold for semiconductor technology as it relates to battery-limited devices like the Apple Watch.

Samsung Said to Supply Apple with NAND Flash Memory in 2017 After Five-Year Hiatus

Samsung is once again set to begin supplying Apple with NAND flash memory chips in 2017, ending a five-year hiatus dating back to the debut of the iPhone 5 in 2012, according to ETNews. The reason for the dissolution of the original supplier relationship is given as Samsung's unwillingness to comply with Apple's electromagnetic interference (EMI) shielding requirements via packaging changes or special coatings on the memory packages themselves. This new claim comes on the heels of an report earlier report, also by ETNews, suggesting Apple was looking to individually shield more parts inside its devices for performance and EMI compliance reasons. The earlier article claimed the impetus for this change was the use of multiple diverse systems such as 3D Touch along with the presence of various high-speed interfaces, all of which can contribute to and be affected by EMI. Individual shielding would also allow Apple to dispense with discrete metal shielding components, which could ultimately save on logic board space and allow more room for other components inside the devices. The new report notes that Samsung's use of ball grid array (BGA) packaging places it at a disadvantage to competing products that use land grid array (LGA) package contacts, which allow the package to sit flush with the printed circuit board. LGA type lead (left) compared to BGA type lead (right) It appears Samsung's existing sputter coat EMI shielding technologies were insufficient for Apple's performance requirements, given the shielding gaps created by the raised BGA contacts. The

AMD's New 400-Series 'Polaris' Graphics Chips Headed for 2016 Macs

Following up on its rumor of a major AMD design win reported last October, WCCFtech has confirmed via multiple sources that the customer in question is indeed Apple. The latest design win follows Apple's use of AMD 200/300 series GPUs in the top-end 27-inch Retina iMac and 15-inch Retina MacBook Pro, and is a boon for the chipmaker that has seen its share of the graphics market dwindle over the past several years. The design wins make mention of two graphics processor families, Polaris 10 and Polaris 11. The former carries a code name "Ellesmere" and is believed to be in the power range that would make it suitable for an upgrade to the iMac. Polaris 11 has the code name "Baffin" and it is believed to be in the power range suitable for an upgrade to the Retina MacBook Pro. While Apple has limited discrete graphics chips to the top of its MacBook Pro and iMac lines, there would be suitable chips for all but the smallest form factors of Apple notebooks, should the company choose to embrace discrete graphics on a broader array of models. As we previously noted, the switch to the new Polaris line of GPUs is set to be a significant performance upgrade over the previous 28nm GPUs. Announced by AMD at Computex, the lower-power AMD GPUs are set to be built on Global Foundries' 14nm process. Through an agreement between multiple foundries, the process is equivalent to Samsung's own second-generation 14nm FinFET process, which is the successor of the process used for the A9 and A9X featured in the latest iPhones and iPads. Performance of these new graphics chips from

Mac Update Cycle Faces Uncertainty as Intel Abandons Tick-Tock Strategy

In its latest 10-K annual report (PDF) filed last month, Intel confirmed the end of its long-heralded "tick-tock" strategy of delivering new microprocessors to the market. Intel originally introduced the product cadence to the world in 2006 with the launch of the "Core" microarchitecture, alternating "ticks" of shrinking chip fabrication processes with "tocks" of new architectures. Over the past ten years, Intel has successively delivered new processor families based on this tick-tock cycle on a nearly annual cycle from its 65 nm manufacturing node all the way up until recently. The tick-tock release cycle allowed Intel to reestablish dominance in both the consumer and enterprise CPU markets and had given OEMs such as Apple a regular update cycle to rely on for annual product updates. But with chip updates stretching about beyond a yearly cycle in recent generations, Apple's product launch cycles have started to be affected. In the face of the difficulties in maintaining the tick-tock cadence, Intel has announced that the launch of Kaby Lake this year as the third member of the 14-nm family following Broadwell and Skylake will mark the official end of the tick-tock strategy. Instead, Intel will move to a new "Process-Architecture-Optimization" model for the current 14 nm node and the 10 nm node. As part of our R&D efforts, we plan to introduce a new Intel Core microarchitecture for desktops, notebooks (including Ultrabook devices and 2 in 1 systems), and Intel Xeon processors on a regular cadence. We expect to lengthen the amount of time we will utilize our 14nm

Apple's Mac Lineups to See Significant Graphics Upgrades as New GPU Launches Loom

Major graphics processing providers AMD and Nvidia are set to unveil new GPU products this year featuring Global Foundries' 14 nm FinFET and TSMC's 16 nm FinFET Plus processor nodes, respectively, allowing for significant improvements in graphics performance. AMD's "Polaris" and Nvidia's "Pascal" architectures both utilize the latest FinFET silicon processes and will represent the first GPU process node change since 28 nm GPUs debuted in 2011. Both AMD and Nvidia skipped the intermediate 20 nm node, elongating the typical release cycle of consumer graphics processors. While TSMC had traditionally provided multiple process offerings within a node, including one specifically tailored to higher power applications such as GPUs, the company found that the traditional planar geometries of its 20 nm node gave the firm less differentiation with its normal set of tweaks, rendering it a poor candidate for power hungry GPUs. In a statement released earlier this year, AMD claimed that the new 14 nm Polaris GPUs will offer over double the performance per watt of their 28 nm predecessors. This news also confirmed AMD's use of Global Foundries' 14 nm FinFET process, rather than TSMC's 16 nm process, which Nvidia will use. While AMD confirmed the use of TSMC for its higher power product offerings, any products developed from that process node would be destined for the Mac Pro only, as Apple has traditionally used mobile GPUs for its notebook and iMac product lines. The new FinFET process nodes promise a big performance jump for AMD's Polaris architecture Product launches

A9X Die Photo From iPad Pro Reveals 12-Cluster Graphics, No L3 Cache

Financial news website The Motley Fool has shared details of the A9X die featured in the new Apple iPad Pro, thanks to analysis from electronics teardown firm Chipworks. The photo reveals the A9X's dual-core CPU and a 12-cluster GPU to drive the device's massive display. While the CPU core count observed in the A9X matches that of the A9 from the iPhone 6s and 6s Plus, the 12-cluster GPU is twice as powerful as the six-cluster GPU found in the A9 design. Otherwise, the core and cluster designs appear to be identical to those found in the A9 die shots. Dual-core CPU boxed in green, six dual-cluster GPU regions boxed in blue Chipworks confirms that the die shown in the photo is fabricated by TSMC, and it does indeed show similarities with the existing A9 TSMC die already pictured by Chipworks. The Motley Fool also points out that the 8 MB third level cache featured on the A9 to help manage data flow to and from memory is not present on the A9X die, suggesting that the absence of this cache is due to the increased memory bandwidth that the A9X enjoys by having a memory interface twice the width of the A9 die. Indeed, in the included die shot, an expansive DRAM memory interface can be observed across three sides of the die. It is also worth mentioning that while the display resolution is much greater than on other iPads, the iPad Pro does not feature the 12-megapixel camera of the iPhone 6s and 6s Plus that would place additional demands on the memory hierarchy for real-time image processing. The presence of only two CPU cores is also interesting, given that

Rumored A10 Production Win for TSMC Could Be Tied to Device Packaging Advances

According to a recent report from Taiwan's Commercial Times, via EE Times and a separate research report from KGI Securities' Ming-Chi Kuo, Taiwan-based TSMC may have won sole production rights on the A10 chip slated for the next-generation iPhone 7. This is in contrast to the split production of the A9 processor between Samsung and TSMC featured in the iPhone 6s and iPhone 6s Plus. Apple's decision to revert back to TSMC as a single supplier, as was seen in A8 chip production, could be motivated by advanced device packaging techniques offered by TSMC that may not have equivalents in Samsung's packaging offerings. The Commercial Times report mentions TSMC's integrated fan-out wafer-level packaging (InFO WLP) technology as one of the key inclusions in the production contract. InFO WLP is one of many competing 3D IC technologies that promise higher levels of component integration in a single package with better electrical characteristics. Among those improvements is the possibility for higher-width memory buses that support lower-power operation necessary for mobile devices, which for consumers means better performance and efficiency. 3D IC technologies are just beginning to emerge in the consumer space, with AMD's use of High Bandwidth Memory (HBM) in its Fiji XT line of discrete graphics cards being one of the first implementations. According to a paper abstract from TSMC engineers, InFO WLP also allows for better thermal performance as well as superior performance for radio frequency (RF) components such as cellular modems. We reported last year about Apple