Chris Jenkins

Chris is a Contributing Writer at MacRumors. An electrical engineer by trade, he likes to spend his free time with family and a hockey game or two.



A Closer Look at Apple's CPU Improvements for iPhone 7 and Apple Watch

At last Wednesday's media event, Apple introduced two new processors - the A10 Fusion for iPhone 7 and 7 Plus and the S2 for Apple Watch Series 2. Although Apple only briefly covered the S2 during the presentation, it did spend a good deal of time talking about A10 Fusion. The 'Fusion' suffix refers to the heterogeneous architecture that the A10 features, which has two high-power, high-throughput cores and two much smaller cores that are more power efficient. Apple also introduced another very important piece of standalone silicon in its new AirPods, dubbed the W1 chip. In total, this represents a great deal of engineering work done by Apple over the last year, and the A10 is the most significant to Apple's system-on-a-chip (SoC) line since the company's transition to 64-bit. Apple unveiled the biggest technical changes featured in the A10 at the very beginning, boasting a four-core CPU with 3.3 billion transistors. While Apple never disclosed a transistor count for the A9, it very likely fell somewhere in the middle between the 2 billion count on the A8 and the 3.3 billion of the new A10. A transistor count well under 3 billion seems probable for the A9; otherwise it would have been worth boasting about on its own. The 3.3 billion number for the A10 is well over 50 percent larger than the A8, and the large jump is likely mostly thanks to the addition of two new, albeit small, CPU cores along with a greatly enhanced image signal processor (ISP). Apple also disclosed that the GPU remains a six-cluster design, while benchmarks suggest that the L1 and L2 cache

Leaked iPhone 7 Logic Boards Suggest Intel Modem, Other Component Tweaks

Last week, MacRumors covered photos of what appear to be the front and rear of bare iPhone 7 logic boards, and since that time we've been able to study these boards and compare them to previous iPhone generations' bare and populated logic boards. Comparing the boards with existing component offerings and information suggests that Apple has indeed moved on from Qualcomm as its baseband modem supplier and switched to Intel for the upcoming iPhone generation. This does not preclude Apple from having other versions of the iPhone 7 or 7 Plus logic boards which feature a Qualcomm modem, such as an international model with differing LTE band options, as has been rumored. Leaked iPhone 7 logic board with Intel modem location annotated The image above shows the previously leaked and annotated logic board front with the probable location of the Intel baseband modem annotated. The pad pattern for the part in this location is markedly different than the pad pattern for the Qualcomm MDM9635, as shown in iFixit's parts catalog. The pad pattern of this mystery part also appears to match the dimensions listed on Intel's website for similar baseband modem offerings to the rumored XMM 7360 design solution.

How TSMC Won Back Exclusivity With Apple for the A10 Chip in iPhone 7

Last year, MacRumors covered the potential reasoning for Apple's rumored return to having a single partner for Apple A-series chip production with the A10 after having both Samsung and TSMC produce versions of the Apple A9. Since then, TSMC confirmed in conference call comments that its chip packaging changes have led to improvements of 20 percent in both speed and packaging thickness and 10 percent in thermal performance. This has a number of implications for future device performance and future foundry partner selection for Apple. First, it is helpful to understand why InFO-WLP (Integrated Fan-Out Wafer-Level Packing) is such an important development for Apple's mobile processors. Typically, chips as large as CPUs or mobile SoCs have been attached via "flip-chip" methods which attach an array of inputs and outputs to a package substrate via solder bumps, ultimately enabling it to be attached to a printed circuit board (PCB) for device integration. From the start, this is a compromise, as it would be preferable to attach a silicon die directly to the PCB to minimize height and reduce the lengths of interconnects between components. A number of technical limits in areas such as interconnect pitch, board produceability, and damage due to board warpage typically prevent this direct attachment. The above problem had previously been circumvented for smaller I/O count components with a similar concept called Fan-In Wafer-Level Packing, where smaller dies are allowed to route their inputs and outputs in an area roughly the same area as the die. TSMC is just one of

New Semiconductor Processes Offer Power Efficiency Opportunities for Apple Watch

One of the key challenges for Apple in developing the Apple Watch was figuring out how to maintain acceptable battery life for the device in the face of power-hungry components such as the main processor and display. With watchOS 3 introduced at WWDC in June, Apple showed off the ability to allow multiple Apple Watch apps to remain active and refresh in the background, acknowledging that its initial approach to managing power and other system resources was conservative but that real-world experience had shown the device could handle more demanding tasks. In addition to software improvements, future generations of the Apple Watch will need to become more efficient on the hardware level, with new versions of the S1 chip that serves as the brains of the device being a primary target for improvement. With that in mind, we've taken a technical look at what the future could hold for semiconductor technology as it relates to battery-limited devices like the Apple Watch.

Samsung Said to Supply Apple with NAND Flash Memory in 2017 After Five-Year Hiatus

Samsung is once again set to begin supplying Apple with NAND flash memory chips in 2017, ending a five-year hiatus dating back to the debut of the iPhone 5 in 2012, according to ETNews. The reason for the dissolution of the original supplier relationship is given as Samsung's unwillingness to comply with Apple's electromagnetic interference (EMI) shielding requirements via packaging changes or special coatings on the memory packages themselves. This new claim comes on the heels of an report earlier report, also by ETNews, suggesting Apple was looking to individually shield more parts inside its devices for performance and EMI compliance reasons. The earlier article claimed the impetus for this change was the use of multiple diverse systems such as 3D Touch along with the presence of various high-speed interfaces, all of which can contribute to and be affected by EMI. Individual shielding would also allow Apple to dispense with discrete metal shielding components, which could ultimately save on logic board space and allow more room for other components inside the devices. The new report notes that Samsung's use of ball grid array (BGA) packaging places it at a disadvantage to competing products that use land grid array (LGA) package contacts, which allow the package to sit flush with the printed circuit board. LGA type lead (left) compared to BGA type lead (right) It appears Samsung's existing sputter coat EMI shielding technologies were insufficient for Apple's performance requirements, given the shielding gaps created by the raised BGA contacts. The

AMD's New 400-Series 'Polaris' Graphics Chips Headed for 2016 Macs

Following up on its rumor of a major AMD design win reported last October, WCCFtech has confirmed via multiple sources that the customer in question is indeed Apple. The latest design win follows Apple's use of AMD 200/300 series GPUs in the top-end 27-inch Retina iMac and 15-inch Retina MacBook Pro, and is a boon for the chipmaker that has seen its share of the graphics market dwindle over the past several years. The design wins make mention of two graphics processor families, Polaris 10 and Polaris 11. The former carries a code name "Ellesmere" and is believed to be in the power range that would make it suitable for an upgrade to the iMac. Polaris 11 has the code name "Baffin" and it is believed to be in the power range suitable for an upgrade to the Retina MacBook Pro. While Apple has limited discrete graphics chips to the top of its MacBook Pro and iMac lines, there would be suitable chips for all but the smallest form factors of Apple notebooks, should the company choose to embrace discrete graphics on a broader array of models. As we previously noted, the switch to the new Polaris line of GPUs is set to be a significant performance upgrade over the previous 28nm GPUs. Announced by AMD at Computex, the lower-power AMD GPUs are set to be built on Global Foundries' 14nm process. Through an agreement between multiple foundries, the process is equivalent to Samsung's own second-generation 14nm FinFET process, which is the successor of the process used for the A9 and A9X featured in the latest iPhones and iPads. Performance of these new graphics chips from

Mac Update Cycle Faces Uncertainty as Intel Abandons Tick-Tock Strategy

In its latest 10-K annual report (PDF) filed last month, Intel confirmed the end of its long-heralded "tick-tock" strategy of delivering new microprocessors to the market. Intel originally introduced the product cadence to the world in 2006 with the launch of the "Core" microarchitecture, alternating "ticks" of shrinking chip fabrication processes with "tocks" of new architectures. Over the past ten years, Intel has successively delivered new processor families based on this tick-tock cycle on a nearly annual cycle from its 65 nm manufacturing node all the way up until recently. The tick-tock release cycle allowed Intel to reestablish dominance in both the consumer and enterprise CPU markets and had given OEMs such as Apple a regular update cycle to rely on for annual product updates. But with chip updates stretching about beyond a yearly cycle in recent generations, Apple's product launch cycles have started to be affected. In the face of the difficulties in maintaining the tick-tock cadence, Intel has announced that the launch of Kaby Lake this year as the third member of the 14-nm family following Broadwell and Skylake will mark the official end of the tick-tock strategy. Instead, Intel will move to a new "Process-Architecture-Optimization" model for the current 14 nm node and the 10 nm node. As part of our R&D efforts, we plan to introduce a new Intel Core microarchitecture for desktops, notebooks (including Ultrabook devices and 2 in 1 systems), and Intel Xeon processors on a regular cadence. We expect to lengthen the amount of time we will utilize our 14nm

Apple's Mac Lineups to See Significant Graphics Upgrades as New GPU Launches Loom

Major graphics processing providers AMD and Nvidia are set to unveil new GPU products this year featuring Global Foundries' 14 nm FinFET and TSMC's 16 nm FinFET Plus processor nodes, respectively, allowing for significant improvements in graphics performance. AMD's "Polaris" and Nvidia's "Pascal" architectures both utilize the latest FinFET silicon processes and will represent the first GPU process node change since 28 nm GPUs debuted in 2011. Both AMD and Nvidia skipped the intermediate 20 nm node, elongating the typical release cycle of consumer graphics processors. While TSMC had traditionally provided multiple process offerings within a node, including one specifically tailored to higher power applications such as GPUs, the company found that the traditional planar geometries of its 20 nm node gave the firm less differentiation with its normal set of tweaks, rendering it a poor candidate for power hungry GPUs. In a statement released earlier this year, AMD claimed that the new 14 nm Polaris GPUs will offer over double the performance per watt of their 28 nm predecessors. This news also confirmed AMD's use of Global Foundries' 14 nm FinFET process, rather than TSMC's 16 nm process, which Nvidia will use. While AMD confirmed the use of TSMC for its higher power product offerings, any products developed from that process node would be destined for the Mac Pro only, as Apple has traditionally used mobile GPUs for its notebook and iMac product lines. The new FinFET process nodes promise a big performance jump for AMD's Polaris architecture Product launches

A9X Die Photo From iPad Pro Reveals 12-Cluster Graphics, No L3 Cache

Financial news website The Motley Fool has shared details of the A9X die featured in the new Apple iPad Pro, thanks to analysis from electronics teardown firm Chipworks. The photo reveals the A9X's dual-core CPU and a 12-cluster GPU to drive the device's massive display. While the CPU core count observed in the A9X matches that of the A9 from the iPhone 6s and 6s Plus, the 12-cluster GPU is twice as powerful as the six-cluster GPU found in the A9 design. Otherwise, the core and cluster designs appear to be identical to those found in the A9 die shots. Dual-core CPU boxed in green, six dual-cluster GPU regions boxed in blue Chipworks confirms that the die shown in the photo is fabricated by TSMC, and it does indeed show similarities with the existing A9 TSMC die already pictured by Chipworks. The Motley Fool also points out that the 8 MB third level cache featured on the A9 to help manage data flow to and from memory is not present on the A9X die, suggesting that the absence of this cache is due to the increased memory bandwidth that the A9X enjoys by having a memory interface twice the width of the A9 die. Indeed, in the included die shot, an expansive DRAM memory interface can be observed across three sides of the die. It is also worth mentioning that while the display resolution is much greater than on other iPads, the iPad Pro does not feature the 12-megapixel camera of the iPhone 6s and 6s Plus that would place additional demands on the memory hierarchy for real-time image processing. The presence of only two CPU cores is also interesting, given that

Rumored A10 Production Win for TSMC Could Be Tied to Device Packaging Advances

According to a recent report from Taiwan's Commercial Times, via EE Times and a separate research report from KGI Securities' Ming-Chi Kuo, Taiwan-based TSMC may have won sole production rights on the A10 chip slated for the next-generation iPhone 7. This is in contrast to the split production of the A9 processor between Samsung and TSMC featured in the iPhone 6s and iPhone 6s Plus. Apple's decision to revert back to TSMC as a single supplier, as was seen in A8 chip production, could be motivated by advanced device packaging techniques offered by TSMC that may not have equivalents in Samsung's packaging offerings. The Commercial Times report mentions TSMC's integrated fan-out wafer-level packaging (InFO WLP) technology as one of the key inclusions in the production contract. InFO WLP is one of many competing 3D IC technologies that promise higher levels of component integration in a single package with better electrical characteristics. Among those improvements is the possibility for higher-width memory buses that support lower-power operation necessary for mobile devices, which for consumers means better performance and efficiency. 3D IC technologies are just beginning to emerge in the consumer space, with AMD's use of High Bandwidth Memory (HBM) in its Fiji XT line of discrete graphics cards being one of the first implementations. According to a paper abstract from TSMC engineers, InFO WLP also allows for better thermal performance as well as superior performance for radio frequency (RF) components such as cellular modems. We reported last year about Apple