New Semiconductor Processes Offer Power Efficiency Opportunities for Apple Watch


watchos_3_dock_lyftOne of the key challenges for Apple in developing the Apple Watch was figuring out how to maintain acceptable battery life for the device in the face of power-hungry components such as the main processor and display.

With watchOS 3 introduced at WWDC in June, Apple showed off the ability to allow multiple Apple Watch apps to remain active and refresh in the background, acknowledging that its initial approach to managing power and other system resources was conservative but that real-world experience had shown the device could handle more demanding tasks.

In addition to software improvements, future generations of the Apple Watch will need to become more efficient on the hardware level, with new versions of the S1 chip that serves as the brains of the device being a primary target for improvement. With that in mind, we've taken a technical look at what the future could hold for semiconductor technology as it relates to battery-limited devices like the Apple Watch.

As transistors begin to reach their physical size limits in modern semiconductor processes, it becomes more difficult, and thus more expensive, to make them smaller. In addition to the cost per transistor no longer shrinking, it also becomes more difficult to control waste power, or leakage. New transistor geometries such as non-planar "3D" FinFETs are becoming popular to address device leakage, but as wearables such as the Apple Watch have begun generating consumer interest, the gains seen in these semiconductor processes are simply still not enough.

For a wearable device such as the Apple Watch, controlling power usage while the device is idle in standby mode is critical to keeping the overall battery life competitive. The need for ultra low power and cheaper silicon processes that are also performance competitive have made way for transistors made with more traditional lithography techniques with higher substrate costs.

The leading candidate technology of this variety is fully depleted silicon-on-insulator, or FD-SOI. FD-SOI technology innovates on traditional "bulk" transistors (seen in Apple devices prior to and including the A8) in two main ways. The first improvement is that the ultra-thin channel on top of the insulating body eliminates the need to dope the channel with additional positive or negative charge carriers, eliminating a source of device variation which can hurt performance optimization. The second improvement is that the insulating body and other characteristics drastically reduce leakage current.

The additional benefits of this process lie in the ability to dynamically control the transistor switching performance by way of biasing the transistor body. This can also be done in traditional bulk type semiconductors, but at the cost of impacting leakage performance. In the case of FD-SOI transistors, the effect is that the performance of the transistors can be modulated in real time.

Modern chips already feature multiple forms of dynamic frequency and voltage scaling (DVFS), but the ability to control FD-SOI transistors is even greater through the use of forward body biasing. Transistors can be dynamically controlled to switch faster by modulating the amount of voltage that must be applied to the device gate to effectively form a channel to operate the transistor.

This dynamic control between forward and reverse body biasing means that the transistors can be operated at extremely low voltages, near the threshold point. Operating at as little as 0.5V, power use can be drastically reduced as device power is often directly correlated with the square (or cube) of applied voltage.

android_watch_batteryThe reason this technology is significant for wearables is because the main system on a chip (SoC) can play such a large part of the device's power consumption, particularly when most usage is idle, as shown in the Android-based example to the right. Reviews have shown that the wrong SoC can absolutely kill a smartwatch's battery performance. The other large factor in a smartwatch's battery usage would be the screen - a component where Apple is much more at the direct mercy of its vendors to provide an acceptably performing product.

Rapid design turnaround from Apple's processor groups, in addition to simultaneous launches of the A9 SoC on competing FinFET processes, show that Apple has the technical bandwidth to commit to introducing an additional design process into its mixture. In fact, we know that the original S1 SoC featured in the debut Apple Watch was manufactured on Samsung's 28nm LP process, in contrast to the leading 20nm process which would have been available at the time.

It is not unreasonable to think that Apple could make a somewhat lateral move to adopt Samsung's 28nm FD-SOI process, which is available now. Further down the road is the possibility of a 22nm FD-SOI process, and the technology will no doubt continue to grow if the market proves the demand as time goes along.

FD-SOI also has tremendous promise for analog and RF circuit applications due to its low leakage characteristics. It would not be a surprise to see RF front-end suppliers such as Qualcomm adopt FD-SOI for their modem and multi-band amplifier applications, and should Apple's hiring of engineers with RF expertise ever come to fruition, it would be a suitable candidate for more custom parts directly from Apple. In any event, do not be surprised if analyses of the next Apple Watch have a few surprises in store when the teardown firms get their microscopes out.

Related Roundups: Apple Watch, watchOS 6, watchOS 7
Buyer's Guide: Apple Watch (Caution)

Top Rated Comments

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51 months ago

As transistors begin to reach their physical size limits in modern semiconductor processes

In 26 years in the semiconductor industry (OK, 19 in the industry, and 7 in aerospace), how many times I've heard sentences start that way, and 3 years later, then laughed at the changes that ingenuity has wrought since that statement was written.
Score: 5 Votes (Like | Disagree)
51 months ago
Nice technical article for a change.

Would like to point out that GloFo has a 22nm FD-SOI available as well.
Score: 2 Votes (Like | Disagree)
51 months ago

the difference is the days you don't or forget to or are out and about without a charge

On days that I forget to charge the AW (e.g., I fall asleep on the couch), the AW battery is small enough that I can easily charge it while getting ready in the am.
Score: 2 Votes (Like | Disagree)
51 months ago

While I understand how you can see that battery life isnt an issue, many of us want a watch that we can wear and not need to charge every day.

"Many of us want a phone that we can use and not need to charge every day."
- A dumbphone owner circa 2007
Score: 2 Votes (Like | Disagree)
51 months ago

Agreed... I keep thinking that we'll find a way to use electron spin and subatomic particles to further the law.

The thing that impressed me was the growing of transistors on layers other than the Silicon base layer. That lets the chips go where they never have gone before: vertical. In that way, the lines can be shorter (instead of having the RAM farm in a certain area, it can just be above the processing area).

Now, as an outsider, it's interesting to see what the engineers come up with, and I know they have the pressure to keep Moore's law.
So, what is stuff made of?
~400 BC - Atomos - Democritus
~350 BC - Earth, Wind, and Fire Aristotle (a fan of disco). Oh yeah, Water left the band early to go solo.
1869 - Atoms of different weights - Mendeleev
1897 - Electrons and other stuff - Johnson
1911 - Electrons and Protons - Rutherford
1913 - Electrons are particles that orbit the nucleus of Protons - Bohr
1926 - Electrons move in a wave form - Schrodinger (and his cat... or not)
1931 - Electrons, Protons, and Neutrons - Chadwick/Rutherford
1964 - Crap... Protons, and Neutrons are made up of other stuff... What about electrons? NO! (well, maybe no) - Mann/Zweig
2017 - ???

The point I'm making is that at each point, there is the question, "how far down can we go?" and there is always one (or more) discoveries that moves that wall. I'm just open to the possibility that there is something else, while keeping in mind the laws of Nature (including subatomic Nature) that are already discovered.

As a side note, when we try to predict how things will turn out, even on things that have no "choice" in the matter, we have to predict how each of those particles will behave. That, in the context of the Chaos Theory, makes everything just a good (or not) guess. All of the wisest people that I've talked to on the subject were the first to admit that what we know would fill a library. What we don't know fills the rest of the universe.
Agreed. In the post above, I put why predicting nature is hard, and predicting individual humans and groups of them is even more difficult. Just look at the 2016 choices: Bad, and Worse. Who is who depends on your point of view...

It may be possible to go smaller, but to keep with the economics of Moore's law is just not realistic with current silicon production methods, Intel added another 14nm stepping for this reason. It's not hard to see we are hitting a limit here.
Again my argument is with current silicon based CPU production within 10 years it'll
1. be too expensive to shrink transistors further
2. even then eventually quantum tunneling is unavoidable

A different fab method which will cost untold billions in R&D and construction of new fab processes will be the end of Moore's law.
I have no doubt will find clever ways around this issue but it's not going to be cheap and it will radically shift the technology sector since everything has been possible because of Moore's law. What happens if CPU's suddenly cost double what they use to?
Score: 1 Votes (Like | Disagree)
51 months ago

In 26 years in the semiconductor industry (OK, 19 in the industry, and 7 in aerospace), how many times I've heard sentences start that way, and 3 years later, then laughed at the changes that ingenuity has wrought since that statement was written.

Silicon atoms have a fixed width, and it's no secret that cost per transistor has flatlined or gone up for some processes. Some vendors are electing to go with higher wafer but lower mask costs in FD-SOI. Some are even skipping some nodes all together. Semiconductors certainly have a future, but it's not in bulk silicon.
Score: 1 Votes (Like | Disagree)

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