Apple's Beats brand in April unveiled the Powerbeats Pro, a redesigned wire-free version of its popular fitness-oriented Powerbeats earbuds.
Apple's Chip Partner TSMC Shares Details on 7nm Node and Advanced InFO Package Process for 2018
At the Open Innovation Platform Ecosystem Forum in Santa Clara on Wednesday, chip foundry TSMC provided an update (via EE Times) on the progress of its forthcoming technology nodes, several of which would be candidates for upcoming Apple chips. Most notably, the company's first 7-nanometer process node has already had several tape-outs (finalized designs) and expects to reach volume capacity in 2018.
TSMC's 10 nm node, which first showed up in Apple's A10X chip in the iPad Pro, followed by the A11, has been fraught with issues (paid link) such as low chip yield and performance short of initial expectations. TSMC looks to change its fortune with the new 7 nm node, which would be suitable for the successor to the A11 chip given current timelines.
In addition to the 7 nm node, TSMC also shared information on the follow-up revision to this node, dubbed, N7+. Featuring the long-beleaguered Extreme Ultraviolet Lithography (EUV), the revision would promise 20 percent better density, around 10 percent higher speeds, or 15 percent lower power with other factors held constant.
While EUV has faced delays for over a decade at this point, it seems to finally be coming to fruition, and a 2019 volume availability update would allow Apple to update its chip process in subsequent years yet again. Apple had previously updated process nodes with every iPhone since the transition to 3GS before being forced to use TSMC's 16 nm node in consecutive years with the A9 and A10. Moving forward, that annual cadence is again in jeopardy as chip foundries deal with the realities of physics and minimum transistor geometry sizes.
TSMC also unveiled some low power and low leakage processes that are suitable for Apple's other custom designs, such as its line of wireless chips like the W1 and successor W2. TSMC is targeting availability next year of a 22 nm ultra low leakage node, which is suitable for analog and RF designs such as cellular basebands or Wi-Fi chips.
This will ultimately help Apple further lower power consumption on the Apple Watch and headphones featuring the W line of wireless chips. It is also likely to be adopted by Qualcomm for its line of modem products. The W1 and W2 manufacturing processes are not currently publicly known, but it is likely that one of TSMC's RF-focused processes powers the Apple chips.
Finally, TSMC announced a revision of its integrated fan-out packaging process (InFO) that is targeted at integrating high bandwidth memory (HBM) into the assembly, dubbed InFO-MS. HBM has generated a lot of interest from applications where very high sustained memory bandwidths are desired, such as consumer graphics cards.
HBM and similar standards such as Wide I/O promise not only to improve memory bandwidth, but also improve power consumption for a given bandwidth, making it a suitable evolution for mobile SoC designs. This type of memory interface has yet to appear in a mobile design, though it should be considered a near-term eventuality. Despite advances in mobile memory, it still lags behind desktop and laptop systems in total bandwidth, which can be important in some tasks such as graphics rendering.
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25 months ago
all it freaking takes is 10 minutes of Jony's time to redesign TSMC's horrid logo. is it that hard?
You want a black notch at the top of the logo ?
25 months ago
all it freaking takes is 10 minutes of Jony's time to redesign TSMC's horrid logo. is it that hard?
You want a black notch at the top of the logo ?
Saved Jony the time of mocking up:
25 months ago
all it freaking takes is 10 minutes of Jony's time to redesign TSMC's horrid logo. is it that hard?
25 months ago
I was thinking the same thing! That logo is straight out of 1972.
I've been a customer of TSMC for over 15 years, and I love their logo: that's what we use TSMC for, to get a wafer back, and we better be aware of yield! (Represented the black -i.e. unworking - squares in the wafer.)As a matter of fact, I was at this conference Wednesday, and a tool vendor concerned with yield made the point that changes in the logo represent (forgetting exact percentage) a 20% increase in yield over the past 10 years :)
25 months ago
all it freaking takes is 10 minutes of Jony's time to redesign TSMC's horrid logo. is it that hard?
I was thinking the same thing! That logo is straight out of 1972.
25 months ago
And yet Apple ships a SoC that is basically the same size as, say, a Kaby Lake dual processor, faster (single and multithreaded), uses less power, has better GPU performance, and includes a whole ton of OTHER useful stuff (like ISP and NPU).
So what exactly is that supposed Intel process advantage getting you? It doesn't result in smaller (or cheaper) chips, or better performance, or more functionality, or lower power.
The ONLY thing it seems good for is producing slides for fanboys.
Seems the performance is not there if you run something other than simple synthetics.
I'd suggest having a read of this if you want to educate yourself on where the different foundry processes currently sit, as the number they stick on it doesn't count for much.
https://www.semiwiki.com/forum/content/6713-14nm-16nm-10nm-7nm-what-we-know-now.html
25 months ago
7nm? What is that, like 30 silicon atoms across? We're getting really close to the end!
"7nm" is marketing. It's just a name for the process technology. The transistors aren't actually 7nm. Think back to "4G vs LTE", 4G was actually 3G, LTE Is actually real 4G.
25 months ago
Perhaps when they launch their 7nm process it will finally catch up with what Intel has been putting out for a few years now.
25 months ago
The relatively low IPC improvement on the A11 shows Apple has gathered most of the low hanging fruit for performance increases.
This 7nm node will be important. With the A11 and A10X not showing much clock increases, it's further evidence 10nm is a half-node step.
This 7nm node will be important. With the A11 and A10X not showing much clock increases, it's further evidence 10nm is a half-node step.
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