The first native benchmarks of Apple's M1 chip appeared on the Geekbench site last week showing impressive native performance. Today, new benchmarks have begun showing up for the M1 chip emulating x86 under Rosetta 2.
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The new Rosetta 2 Geekbench results uploaded show that the M1 chip running on a MacBook Air with 8GB of RAM has single-core and multi-core scores of 1,313 and 5,888 respectively. Since this version of Geekbench is running through Apple's translation layer Rosetta 2, an impact on performance is to be expected. Rosetta 2 running x86 code appears to be achieving 78%-79% of the performance of native Apple Silicon code.
Despite the impact on performance, the single-core Rosetta 2 score results still outperforms any other Intel Mac, including the 2020 27-inch iMac with Intel Core i9-10910 @ 3.6GHz.
Initial benchmarks for the MacBook Air running M1 natively featured a single-core score of 1,687 and multi-core score of 7,433. Additional benchmarks with M1 have since surfaced and are available on Geekbench.
Meanwhile, a full chart of Geekbench results is available that will let you compare these scores to any other Mac.
Top Rated Comments
Massive reorder buffer: UltraSparc V had that. I know, because I was the original designer of the reorder unit on that chip.How about the width compared to other silicon (and yes, I’m aware x86 struggles on width due to its instruction set baggage), the massive reorder buffer, the large number of dedicated units for processing or accelerating single tasks in parallel with the cpu, the on die memory? There are other deviations too, but then again you can easily educate yourself on that if you so wish without me spouting off about it. There are large deviations in this chip from the normal train of thought and standard processor design. But feel free to inform me of chips that have this style of architecture if you know of any, I’m happy to see hard facts.
On die memory: there is no on die memory. It’s in the package, but not on the die. This is easy to see from the actual die photographs that have appeared on Ars (I addressed this claim in another thread and posted the picture). There are a number of LPDDR4X channels with off-chip drivers, so you can even see how the die connects to off-die RAM. Here’s the photo: https://images.anandtech.com/doci/16226/M1.png
”width”: what width are you referring to? There is nothing unusual about the execution width. It’s, in fact, identical to that used in, say Athlon-64 and Opteron. (I know, because I owned the integer execution unit for the first of those designs)
Dedicated units: most chips are now designed as SoC with on-chip encryption units, etc. AMD transitioned to that design methodology with Bulldozer. I know, because I left AMD right around when that started happening.
The CPU portion of the chip is very similar to every other CPU I ever designed. The SoC methodology is now a very common methodology.
What’s different here is competence, not some radical difference between M1 and x86 chips.
How can you say “for seemingly no good reason?”no honestly the only complaint here is in how closed this system is going to become and for seemingly no good reason.
but M1 looks like a legit beast.
It’s got way more performance than any of the competition, and two or three times the battery life.
Aren’t those good reasons?
Oh, I know. They’ll fall back to “but it doesn’t virtualize x86.”
Anyway, that’s actually more of a Rosetta-speed hit than I expected, but we’ll see when we get real world data.