Apple's Huge 3nm Chip Orders for iPhone 15 Pro and M3 Macs Helping to Maintain TSMC's Fab Utilization Rates

The industry is moving from nm to Ångströms. The node after 2 nm will be 18 å for example.

I'll finally find a use for this key on my Finnish keyboard.

What is the actual transistor size? I haven't been following that closely these past few years.

From Wikipedia:

The term "5 nm" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors being 5 nanometers ('https://en.m.wikipedia.org/wiki/Nanometer') in size. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems ('https://en.m.wikipedia.org/wiki/International_Roadmap_for_Devices_and_Systems') published by IEEE Standards Association Industry Connection, a "5 nm node is expected to have a contacted gate pitch of 51 nanometers and a tightest metal pitch of 30 nanometers".[3] ('https://en.m.wikipedia.org/wiki/5_nm_process#cite_note-3') However, in real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process ('https://en.m.wikipedia.org/wiki/7_nm_process').

https://en.m.wikipedia.org/wiki/5_nm_process

The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems ('https://en.m.wikipedia.org/wiki/International_Roadmap_for_Devices_and_Systems')published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.[14] ('https://en.m.wikipedia.org/wiki/3_nm_process#cite_note-14')However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[15] ('https://en.m.wikipedia.org/wiki/3_nm_process#cite_note-15')[16] ('https://en.m.wikipedia.org/wiki/3_nm_process#cite_note-16') Moreover, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. Typically the chip manufacturer refers to its own previous process node (in this case the 5 nm process ('https://en.m.wikipedia.org/wiki/5_nm_process')node) for comparison. For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25-30% at the same speed, increase speed by 10-15% at the same amount of power and increase transistor density by about 33% compared to its previous 5 nm FinFET chips.[17] ('https://en.m.wikipedia.org/wiki/3_nm_process#cite_note-17')[18] ('https://en.m.wikipedia.org/wiki/3_nm_process#cite_note-18') On the other hand, Samsung has stated that its 3 nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process.

https://en.m.wikipedia.org/wiki/3_nm_process

3 nanometer circuits... I still find this amazing. The first processor I ever experimented with was at 3500 nm. Not a typo.

From Wikipedia:


https://en.m.wikipedia.org/wiki/5_nm_process

Holy crap! It's marketing BS ?

I thought something was off. Years ago I remember reading that below 5nm might be impossible due to quantum effects / hard physical reality.

Obviously marketing doesn't have those limitations.

3 nanometer circuits... I still find this amazing. The first processor I ever experimented with was at 3500 nm. Not a typo.

it doesn’t seem real because it isn’t. The whole nm thing largely lost meaning and it has little to do with the actual transistor size. Sure there has been huge progress and they can squeeze so many more transistors in the same area than they used to, but 3nm is a misleading number. The truth is that we got to the limit of what’s physically possible: silicon atoms have a size and you can’t change that fact no matter how much research you do.

Does anyone else see what’s happening here? Eventually the nm will require floating point numbers, and these devices will be in more everyday devices running chatGPT 10.0 and replace us (although I think 100-200 year timeline on that last part, if not 5000).

The industry is moving from nm to Ångströms. The node after 2 nm will be 18 å for example.