Apple chipmaker TSMC has set out the potential performance and power efficiency of the upcoming iPhone 12's A14 chip, according to a report by AnandTech.
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The iPhone 12 is expected to contain an A14 chip, based on TSMC's smaller 5nm manufacturing process. The iPhone 11's A13 chip used a 7nm process by comparison.
Manufacturing chips using this smaller process offers a number of advantages, including a reduction in power consumption of up to 30 percent, and up to 15 percent increased performance. This indicates what kind of improvements may come to the A14 chip in the iPhone 12.
There is a tradeoff when selecting one or the other, but Apple tends to prioritize performance improvements over power consumption. When reducing the size of the manufacturing process for a new generation of chips, power consumption and performance improvements are slightly lower.
Last year, TSMC announced a $25 billion investment in the new 5nm node technology in a bid to remain the exclusive supplier of Apple's processors. TSMC has reportedly been in mass production of chips using the 5nm process for several months now, and the process is also expected to be used for Apple Silicon chips coming to the Mac before the end of this year.
In addition to the 5nm process for 2020, TSMC outlined its plans for a 3nm process coming in late 2022. This would likely be used for a potential A16 chip and other future Apple Silicon if the company follows previous years, but it is understandably difficult to speculate on Apple's manufacturing plans so far ahead. The 3nm process yields similar 30 percent and 15 percent power consumption and performance improvements over the 5nm process.
It is worth noting that regardless of the performance of TSMC's chips, Apple usually optimizes its software for further performance improvements. It is also possible that Apple could significantly prioritize power consumption over performance for improved battery life. These decisions belong to Apple regardless of TSMC's manufacturing process, making the exact behavior of the A14 chip somewhat uncertain until official announcement.
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I think it's supposed to suggest that performance and power consumption gains are becoming less pronounced at each new stage.It’s gibberish.
[IMG alt="Shows a graph of performance and power-consumption improvements."]https://spectrum.ieee.org/image/MzMwNzU1Ng.jpeg[/IMG]
https://spectrum.ieee.org/semiconductors/devices/another-step-toward-the-end-of-moores-law
We are about to hit the atomic limit of process nodes.
Conceivably, if nodes keep being reduced by roughly 1/2 for the next decade, we'll enter the atomic range soon:Nope. They told me that in 1992, too. :)
0.2 nm or so for silicon, yes? Got a ways to go. And, of course, the process node “size” has very little to do with the actual size of actual devices. I don’t think I ever used a minimum length transistor.
2019: 5nm
2022: 3nm
2025? 1nm - 1.5nm?
Then we enter picometers.
2030? 500pm - 750pm? (.5nm - .75nm)
Depending on the atom, that's anywhere from 50pm - 500pm in size. Basically, silicon's days will be numbered once we reach the 2030s.
It’s gibberish.I don't understand this statement in the third sentence. In two other places it says smaller = faster and more efficient...so what's up with this part? "When reducing the size of the manufacturing process, power consumption and performance improvements face a slight reduction."
It’s also not true that smaller necessarily means faster and more efficient, but that’s just me being pedantic.