TSMC Reportedly Completing Designs for 10-nm A11 Chip With Early 2017 Availability

Taiwan Semiconductor Manufacturing Company (TSMC) has begun to "tape out" the design for Apple's A11 processor built on a 10nm FinFET process, according to industry sources (via DigiTimes). Taping out refers to the initial design of the chip having been completed for creation of the masks that will be used to print the actual chips, although further tweaks are likely as test production is carried out.

Following the final result of the design cycle for the A11, TSMC is expected to achieve certification on its 10nm manufacturing process in the fourth quarter of 2016, and deliver product samples to Apple for validation in the first quarter of 2017. TSMC is expected to obtain about two-thirds of its overall A11 chip orders directly from Cupertino.

The same sources indicate that TSMC could begin small-volume production for Apple's A11 chips as early as the second quarter of 2017, which would generate revenue for the company in the following quarter.

Apple currently operates a two-year upgrade cycle for its smartphones. All things remaining the same, that would mean the A11 would be headed for the "iPhone 7s", the likely successor to the next-generation iPhone 7 which is slated to launch this fall. However, last month Barclays analyst Mark Moskowitz speculated Apple will skip its traditional "S" upgrade cycle next year altogether.

Citing industry sources, Moskowitz said the Cupertino company won't debut a spec-bumped, internally upgraded "iPhone 7s" in 2017, but a completely overhauled "iPhone 8" with "major design changes" and new, next-generation features like wireless charging. Either way, the A11-powered iPhone models would therefore be expected to launch in the second half of 2017.

In February, TSMC reached a deal with Apple to be the sole manufacturer for the A10, which is expected to be the processor included in the iPhone 7 and iPhone 7 Plus. The deal was thought to have been motivated by TSMC's advanced device packaging techniques capable of higher-width memory buses and lower-power operation, which for consumers means better performance and efficiency.