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Quicksilver Benchmarks, etc.
...note as mentioned here before - the L3 cache is DDR, so the effective rate is 1/2 the CPU speed, not 1/4. I suspect the removal of the L3 cache on the new 733 is just a cost cutting measure...
I remember reading that they did away with a lot of chips in the new board related to the bus in an effort to reduce latencys, etc. in a interview done with one of the Apple higher ups at MWNY.
The DDR L3 cache may come as news to some. (DDR provides its namesake "double data rate" by allowing memory access on both the leading and trailing edges of the clock.) This mention of an optimized board design goes against recent news that the optimizations mentioned here yesterday were also present on the "old" G4 733.