Apple Using HyperTransport?
CNet reports that Apple Computer is planning to discuss their use of HyperTransport at WWDC:
The Cupertino, Calif.-based company will use HyperTransport as a high-speed link between the two processors that make up the chipset in new desktop Macintoshes, sources said. A chipset is a group of chips that manages the internal functions of a computer.
According to the article, Hypertransport 1.0 allows for data transfer rates of "6.4 gigabytes to 12.8 gigabytes" [ed note: per second] and while definite ship dates for new computers are unclear, they expect that "it should not be too long" before the technology makes it into new Macs.
Based on recent rumors, Apple is widely expected to utilize the PowerPC 970 chip from IBM in future computers, and is expected to discuss this technology at the WWDC. MacBidouille is expecting the use of Hypertransport, as well as DDR 400, USB 2.0 and AGP 8x in upcoming PowerMacs.
Hypertransport is also being used by AMD, and is described as eliminating bottlenecks in existing systems in this earlier CNet article:
- In HyperTransport servers, the central bus is eliminated. Instead, processors and memory are spread out and united by a high-speed ring road, similar to the decentralized live-work areas that have become common in high-population areas. Memory latency, or the time gap between when a processor requests data and when it actually retrieves it from memory, are reduced, according to AMD executives and various analysts.
Related Link: Hypertransport.org
Top Rated Comments
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113 months ago
I think that this is awesome. If Apple wants to get back in the race they are going to utilize the newest technology as quickly as possible.
P-Worm
P-Worm
113 months ago
I do remember C|Net jumping the gun on a few rumors in the past, so, as always, understand that this may not be entirely true.
I'll try to dig up C|Net's previous foul-ups on Apple rumors.
I'll try to dig up C|Net's previous foul-ups on Apple rumors.
113 months ago
hmmm... I think this is in a way a bad thing. only because "it should not be too long" seems like it could mean that there will be a revision between now and when it is used.
113 months ago
Originally posted by rice_web
I do remember C|Net jumping the gun on a few rumors in the past, so, as always, understand that this may not be entirely true.
I'll try to dig up C|Net's previous foul-ups on Apple rumors.
You are probably right about cNet screwing up a couple of times, but for me, this is the most reliable source that we have gotten G5 info from. The sources of have gotten much more credible over the last few days. From MacB to MacWhispers to eWeek and now to cNet. :)
113 months ago
This technology is nice. Its an interconnect with room to grow as the 970, 980 blossom.
This tech poses significant relevance to developers, so the WWDC WOULD be the place to discuss this.
So, following my rusty logic, if they discus hypertransport, then they let the cat out of the bag that new Macs are on the way. So it looks like they just may demo new stuff.
But I must still be a hard dose of reality and say that we are looking at early August at best for actually getting one of these in our hot little hands.
This tech poses significant relevance to developers, so the WWDC WOULD be the place to discuss this.
So, following my rusty logic, if they discus hypertransport, then they let the cat out of the bag that new Macs are on the way. So it looks like they just may demo new stuff.
But I must still be a hard dose of reality and say that we are looking at early August at best for actually getting one of these in our hot little hands.
113 months ago
Thus the need for smeagol. Many people were so hung up on the new 10.2.7 code named smeagol enabling 64 bit functionalitly. But the 970s from what I understand do 32 bit natively, so no need for rewrites in software.
However, if you are using Hypertransport, and want to enable a new chipset. You need an OS that supports the new chips, and technology, thus the Smeagol. Just my take on it of course, but that makes more sense to me.
However, if you are using Hypertransport, and want to enable a new chipset. You need an OS that supports the new chips, and technology, thus the Smeagol. Just my take on it of course, but that makes more sense to me.
113 months ago
Hey Arn--
I'm not sure if this would work out, and I don't want to cause any political tension between sites or anything, but it would be really helpful to have something like a "buyers guide" for rumor site reliabilities.
You could go through different rumor sites, their predictions, the reality of those predictions, and then how credible a source that rumor site is. That would be really useful in determining validity of different rumors?
Cheers,
ReeD.
I'm not sure if this would work out, and I don't want to cause any political tension between sites or anything, but it would be really helpful to have something like a "buyers guide" for rumor site reliabilities.
You could go through different rumor sites, their predictions, the reality of those predictions, and then how credible a source that rumor site is. That would be really useful in determining validity of different rumors?
Cheers,
ReeD.
113 months ago
Newsfactor also has an article stating that Apple will be using Hypertransport (and an AMD chipset) in the forthcoming Powermas:
"According to preliminary reports -- completely unsubstantiated by Apple -- the G5 will be turbo-charged with IBM's (NYSE: IBM - news) 64-bit PPC 970 processor. The system's 64-bit addressing will be a major step past Apple's current bus architecture. The new machines will also include AMD's (NYSE: AMD - news) Hypertransport technology, which can push data down pipes at speeds in the neighborhood of 12.8 Gigabytes per second. "
For the complete article: http://story.news.yahoo.com/news?tmpl=story&u=/nf/20030612/bs_nf/21715
We'll see soon, I guess....
"According to preliminary reports -- completely unsubstantiated by Apple -- the G5 will be turbo-charged with IBM's (NYSE: IBM - news) 64-bit PPC 970 processor. The system's 64-bit addressing will be a major step past Apple's current bus architecture. The new machines will also include AMD's (NYSE: AMD - news) Hypertransport technology, which can push data down pipes at speeds in the neighborhood of 12.8 Gigabytes per second. "
For the complete article: http://story.news.yahoo.com/news?tmpl=story&u=/nf/20030612/bs_nf/21715
We'll see soon, I guess....
113 months ago
I'm sooo glad these journalists know more than the gang at arstechnica, who are still trying to get info on exactly what type of bus IBM is using on the 970. :rolleyes:
Spiffy, for them to say IBM has choosen AMDs HyperTransport instead their own (Motorola's) Rapid IO bus for multi-CPU 970 designs. Considering the CPU design would spec out what bus is used for feedback for the cache/memory snooping.
Or are they just relying on bus speeds rates to say it's HT. :rolleyes:
Of course the bus used for the FSB as we know it wouldn't really rule out HT in the rest of the system, especially since there are off-the-shelf chipsets available to graft onto.
---
Hannibal should be talking to the IBM PPC 970 architects sometime to get an idea of the SMP topology, and some of the nitty-gritty details answered. When is the question...
Spiffy, for them to say IBM has choosen AMDs HyperTransport instead their own (Motorola's) Rapid IO bus for multi-CPU 970 designs. Considering the CPU design would spec out what bus is used for feedback for the cache/memory snooping.
Or are they just relying on bus speeds rates to say it's HT. :rolleyes:
Of course the bus used for the FSB as we know it wouldn't really rule out HT in the rest of the system, especially since there are off-the-shelf chipsets available to graft onto.
---
Hannibal should be talking to the IBM PPC 970 architects sometime to get an idea of the SMP topology, and some of the nitty-gritty details answered. When is the question...
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